1. Field of the Invention
The invention relates to a composite thermal detector array comprising an array of discrete thermal detector elements. The array may be a linear or a two-dimensional array. Linear arrays are particularly suitable for applications where there is relative motion between the detector head and any objects being imaged. Two-dimensional detector arrays are used in a wide range of infrared imaging applications.
2. Discussion of Prior Art
Thermal detectors such as ferroelectric detectors and resistance bolometers are of interest due to their operation at ambient temperatures unlike the photon (or semiconductor) detectors which require cryogenic modules for cooling. Development of thermal detectors is currently directed towards the achievement of arrays having large numbers of elements with small inter-element pitch and to enhancing the level of temperature discrimination that may be observed in the scene above the inherent noise level in the detector array and the imaging system designed for the viewing of the video image.
Linear and two-dimensional arrays of thermal detectors have been constructed using, as the radiation sensitive element, both ferroelectric materials and also resistance bolometer materials, the latter from a range of oxide, metal and semiconductor materials. Ferroelectric wafers prepared from ceramic blocks and polished to thin sections have been bonded to the silicon readout integrated circuitry (IC) directly by metal bump bonding as described in U.S. Pat. No. 4,142,207. This patent further emphasises the desirability of improving the thermal isolation of the detector element from the silicon IC by bonding to the top of thin metal columns fabricated on the silicon IC, one for each element. Improved thermal isolation (i.e. low thermal conductance to the element) is necessary to secure high responsivity from the element when absorbing infrared radiation focused from the scene. The bump bonding process may involve a cold-weld between metal surfaces or a solder bump bond between wettable metal pads on the element and the input circuitry of the silicon IC [D J Pedder, Hybrid Circuits, Vol. 15. p4, 1988].
In U.S. Pat. No. 5,450,053 the thermal isolation of the detector elements is obtained by the construction of arrays of microbridge structures on the surface of the silicon readout integrated circuitry (ROIC) such that there is one microbridge per element. The microbridge supports the detector element above the IC on thin and narrow legs to achieve the low thermal conductance. The detector element material is deposited as a thin film on or as the microbridge structure and is provided with suitable electrodes to collect the signal and pass this down the legs to the silicon readout circuitry in the IC. The technique of depositing resistance bolometer material enables the fabrication of a large array of resistance micro-bolometers. The technique enables the fabrication of higher performance detector arrays than those fabricated using the bump bonding technique due to the lower thermal conductances that may be achieved.
It has been proposed [R. Watton, Ferroelectrics, Vol. 133, pp. 5-10, 1992] that ferroelectric thermal detector arrays of high performance may be fabricated using microbridge structures. The ferroelectric material may be deposited by various techniques, sol-gel processing, rf magnetron sputtering, laser ablation or MOCVD. However, a severe limitation in the deposition of the ferroelectric film onto the microbridge structures is the limit on the temperature that the silicon IC, which acts as substrate with the array of microbridge structures, can be raised to during the deposition. The silicon IC maximum temperature is restricted to the region of 500xc2x0 C. to avoid damage to the circuitry providing the array readout functions (i.e. amplification and element matrix switching). However is has been proposed that to achieve good ferroelectric properties in the deposited ferroelectric film high substrate temperatures may be required either in the deposition process or in subsequent annealing [R Watton, ibid. and R Watton, Integrated Ferroelectrics, Vol. 4, pp175-186, 1994].
U.S. Pat. No. 3,801,949, relates to a thermal detector device in which an array of detector elements is fabricated on a silicon substrate containing the readout circuitry for the detector elements. A thin layer of silicon dioxide, deposited on the substrate, thermally insulates the substrate from the detector elements during detection of infrared radiation. The detector elements are fabricated on the substrate containing the detector readout circuitry prior to the etching of openings in the substrate which also serve to thermally isolate the detector elements from the circuitry during detector operation. However, as described previously, the problem exists that the silicon substrate containing the readout circuitry cannot withstand the elevated temperatures required to fabricate detector elements having good ferroelectric properties.
It is known that there exists an incompatibility between the temperatures required in the deposition or annealing of the ferroelectric films, to obtain the most favourable properties for thermal detector arrays, and the temperature limits set by avoidance of damage to the metallisation and circuits on the silicon readout IC. For example, annealing sputtered films of the ferroelectric lead scandium tantalate to temperatures between 800xc2x0 C. and 900xc2x0 C. results in ferroelectric properties in the films which approach those measured in the ceramic material used in the bump bonded technology described previously [R Watton and M A Todd, Ferroelectrics, Vol. 118, pp279-295, 1991]. Such values of ferroelectric properties, if combined with the higher thermal isolation of the microbridge element structures, would result in very high performance thermal detector arrays.
It has also been proposed that ferroelectric films of both lead zirconate titanate and lead scandium tantalate can be deposited or annealed at temperatures in the region of 500xc2x0 C. but with reduced values of those ferroelectric properties which determine the imaging performance of thermal detector arrays [R Watton, Ferroelectrics, Vol. 184, pp 141-150, 1996]. The reduced values do not preclude a useful imaging performance from arrays prepared by these processes but significant improvements in performance will be available if the temperature limitation were removed.
The temperature limitation problem outlined above is overcome by the present invention. The invention relates to a composite structure for thermal detector arrays which allows the fabrication of ferroelectric element arrays on microbridge structures at higher temperatures than those presently allowed by the limitation of avoidance of damage to the readout integrated circuitry.
According to one aspect of the invention, a thermal detector device comprises;
an array of thermal detector elements for detecting infrared radiation and generating output detector signals,
an array of microbridge structures comprising said detector elements, wherein each microbridge structure also includes a common contact and an output contact, wherein each of the common contacts is in electrical contact with each of the other common contacts,
readout integrated circuitry having a plurality of input contacts, for processing the output detector signals,
and an interconnect layer, having front and rear surfaces, thermally isolating the array of microbridge structures from the readout integrated circuitry and comprising a plurality of interconnect channels between said front and rear surfaces, wherein the interconnect channels provide an electrical connection between the output contact of each of the microbridge structures and the associated input contact on the readout integrated circuitry such that the microbridge structures are in electrical contact with, but are separated from, the readout integrated circuitry
wherein the interconnect layer is a wafer which supports the array of microbridge structures during fabrication of the latter and wherein the input contacts of the readout circuitry are substantially vertically aligned with the output contacts.
At the rear face of the interconnect layer, the interconnect channels may be bump bonded to the input contacts of the readout integrated circuitry.
In addition to the detector elements, each microbridge structure may also comprise additional support layers. Additional support layers may be required, in particular, for microbridge structures comprising thin detector elements which do not provide sufficient support themselves.
In a preferred embodiment, the detector elements may be comprised of a ferroelectric material. The interconnect channels may each comprise a channel of electrically conducting material, for example polysilicon or an electroplated, chemically plated or vapour deposited metal. Each interconnect channel may further comprise a channel of dielectric material for electrically isolating the conducting material from the interconnect layer material. Typically, the dielectric material may be an oxide or a nitride layer formed from the interconnect layer material.
The interconnect layer may be any one of silicon, glass or a ceramic material or any other material capable of supporting conducting channels in the interconnect layer. Alternatively, the interconnect layer may be electrically conducting or semi-conducting material. Preferably, the interconnect layer material is thermally matched in thermal expansion properties to the underlying silicon layer.
Typically, each of the detector elements may have an electrical capacitance of between 1 picofarad and 1 nanofarad and, preferably, the electrical capacitance of each interconnect channel is at least less than one tenth of the electrical capacitance of each ferroelectric detector element.
According to a second aspect of the invention, a method of fabricating a thermal detector device comprises the steps of;
(i) providing an interconnect layer having front and rear surfaces, wherein the interconnect layer is a wafer comprising a plurality of interconnect channels between said front and rear surfaces,
(ii) fabricating an array of thermal detector elements as an array of microbridge structures on the interconnect layer, wherein each microbridge structure includes a common contact and an output contact, each of the common contacts being in electrical contact with each of the other common contacts and each interconnect channel being in contact with the output contact on one of the microbridge structures, and
(iii) subsequently bonding the interconnect channels at the rear surface of the interconnect layer to readout silicon integrated circuitry, such that the microbridge structures are in electrical contact with, but are separated from, the readout integrated circuitry.
The method may further comprise the step of fabricating at least one additional support as part of the microbridge structures. The interconnect channels may be formed by a reactive ion etch technique.
The thermal detector elements may be fabricated as part of the microbridge structures by means of a deposition process. The fabrication of the array of thermal detector elements may also include the step of annealing the thermal detector elements. Preferably, at least one of the deposition process or the annealing process is carried out at a temperature well above the limiting temperature which applies to processing directly on the silicon readout wafer. For example, at least one of the deposition process or the annealing process may be carried out at a temperature of at least 500xc2x0 C. and, more preferably, at a temperature of at least 700xc2x0 C.